1. Field of the Invention
The present invention relates to the field of data transfer. More particularly, the present invention relates to a circuit and method for replacing address translations contained in an address translation unit.
2. Description of Art Related to the Invention
For over a decade, a number of system architectures have been developed with input/output ("I/O") devices accessing main memory through direct virtual memory accesses using virtual addresses, instead of direct memory accesses ("DMAs") using physical addresses. One advantage associated with DVMA systems has been the simplification of data accesses by the I/O device. For example, I/O devices accessing memory through DMAs ("DMA I/O devices") must be controlled to "scatter" (or allocate) data to a number of potentially discontiguous physical pages as well as to "gather" data. Gathering data that exceeds one page in length is normally accomplished by accessing a group of discontiguous physical pages. In contrast, I/O devices that access main memory through DVMAs ("DVMA I/O devices") do not require such control because data accesses are made through contiguous virtual pages.
Although the DVMA systems have simplified this "scatter-gather" problem, these systems require the virtual addresses issued by the DVMA I/O devices to be translated into physical addresses before data can be accessed from main memory. As shown in FIG. 1, a conventional DVMA system 100 utilizes an I/O Memory Management Unit "I/O MMU" 110, sometimes referred to as an I/O Translation Lookahead Buffer, to translate virtual addresses to physical addresses utilized by main memory 120. As shown, the I/O MMU 110 is implemented within a bridge element 130 that couples an I/O bus 140 and a system bus 150.
Typically, the I/O MMU 110 is often configured to contain a limited number "r" of address translations (e.g., 16 fully-associative entries) to increase system performance with minimal additional costs. Thus, a plurality of I/O DVMA devices 160.sub.1 -160.sub.i ("i" being a whole number, i.gtoreq.2) are restricted to collectively use at most "r" virtual pages without mitigating system performance. If a requested address translation is not contained within the I/O MMU 110, resulting in an I/O MMU "miss", the requested address translation must be fetched from main memory 120 which contains all potential address translations. Of course, such fetching reduces system performance.
With the emergence of multi-media communications, networks are now being required to support multiple data types. As a result, network manufacturers are tending to concentrate their efforts toward asynchronous transfer mode ("ATM") networks. In ATM networks, a large number of virtual channels, perhaps hundreds, can be in operation simultaneously. Hence, if the DVMA system 100 is configured to support an ATM network coupled to I/O network interface logic 170, it would experience significant performance degradation caused by excessive fetching of address translations from main memory.
Hence, it would be advantageous to develop an address translation unit ("ATU") implemented within and operating in cooperation with a Network Interface Circuit ("NIC") coupled to the I/O bus. The MC would be used to interconnect the ATM network environment to the DVMA system. More particular to the present invention, it would be advantageous to develop replacement circuitry, being a minimal amount of additional logic that operates in combination with the ATU, to control the loading and replacement of address translations contained in predetermined entries within the ATU. The primary purpose of the replacement circuitry would be to reduce the amount of time that an entry remains in the ATU after accesses to its affiliated virtual page have ceased, and to replace the contents of "valid" entries only if no "invalid" entries are available.